An Adaptive Physical Channel Regulator for High Performance and Low Power Network-On-Chip Routers

Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMP architectures, where wires become abundant resources available inside the chip. NOC must be carefully designed to meet constraints of power and area, and provide ultra low latencies. In this paper, we propose an Adaptive Physical Channel Regulator (APCR) for NOC routers to exploit the huge wiring resources for high performance and low power. The flit size in an APCR router is no longer equivalent to the physical channel width (phit size) providing finer granularity flow control. An APCR router allows flits from different packets or flows to share the same physical channel in a single cycle. The three regulation schemes (Monopolizing, Fair-sharing and Channel-stealing) intelligently allocate the output channel resources considering not only the availability of physical channels but the occupancy of input buffers. In an APCR router, each Virtual Channel can forward dynamic number of flits every cycle depending on the run-time network status. We also introduce Generalized NOC Router Design (GNRD) – a frame-work for exploring the design space of NOC routers. Our simulation results using a detailed cycle-accurate simulator show that an APCR router improves the network throughput by over 100%, compared with a baseline router design with the same buffer size. An APCR can outperform the baseline router even if the buffer size is halved. Furthermore, an APCR router enjoys over 33% total power savings with a little area overhead.